3Rd grade dra levels

August 30, 2021

by Beth Gorden

Anyone else completely confused by reading levels? There are guided reading levels, Lexile numbers, and Book Levels like the library uses. I found this especially confusing when my kindergarten and grade 1 students were beginning to read. I assumed you just get a beginner reader, but guess what – it’s NOT that easy! Many beginner readers are actually for 3rd graders! YIKES! Don’t worry, I can explain reading levels, give you book recommendations by grade, and take all the work out of finding your child the best books to read by reading level!

Making Sense of Reading Levels

What Level Books should my Child be reading by Grade!

I think one needs a masters degree in nonsense to make sense of reading levels! Seriously there are 3 different systems used: Lexile, Book Level (like most libraries) and Guided Reading (Scholastic) that parents must try to understand. And if you google it, there isn’t much useful information out there either.

I even talked with my local librarian who gave me a lot of misinformation, ugh! So I did deeper research so I could pick out readers for my kids.

Reading levels by grade

I don’t claim to be an expert on reading levels by any means, but for all you confused parents here is some help from a mom that was just as confused as you are!

Note: All kids read at their own pace and this is just an average generalization. Please work on reading books at your child’s reading level. For kids who are great readers, they may be reading at books above their reading level.

Kindergarten Reading Level

Kindergartners are just beginning to read using some basic sight words and decoding simple words. In the library look for books labeled 0.1 – 1.3.  For those using the Scholastic Guided Reading level, look for A, B, or C. (That is 25-75 in Lexile). Remember they need 30 minutes of daily reading; practice makes perfect!

• 50 Books for Kindergartners to Read by Themselves
• 45 Must Read Books for Kindergartners (Read Aloud)

First Grade Reading Level

1st Grade students are decoding more words, learning rule breaker rules, and adding more and more sight words. Through the course of the year they can be anywhere from a 1.0 – 1.9 for readers at the library. For those using Scholastic Guided Reading that is B-I or Lexile 50-275. Remember they need 30 minutes of daily reading; practice makes perfect!

• 100 Books for 1st Graders to Read Themselves 
• Favorite 1st Grade Read Aloud Picture Books
• 17+ 1st Grade Read Aloud Chapter Books you won’t want to miss!
• Top 25 Chapter Book Series for 1st-3rd Grade

2nd Grade Reading Level

2nd Graders are reading well independently. Although they may start their year in advanced readers, most are ready for simple chapter books by the end of the year. Just like Kindergarten and 1st graders, they need lots of practice to continue advancing. Even though 2nd graders are reading well on their own, they still need time reading aloud to an adult who can help them correct pronunciation, flow, and check reading comprehension to ensure no issues creep up. At the library look for books labeled 1.6-2.9. Using a Guided Reading system look for H-M or 225-450 in Lexile.

• Best 2nd Grade Reading List
• 2nd Grade Read Aloud Chapter Books
• Top 25 Chapter Book Series for 1st-3rd Grade

3rd Grade Reading Level

3rd Graders are comfortable reading simple chapter books on their own. They continue to need lots of practice and time reading aloud as well. At the library look for books 2.2 – 3.9, Guided Reading level L-P, and Lexile 400-650.

• 3rd Grade Reading List
• Top 25 Chapter Book Series for 1st-3rd Grade

4th-8th Grade Reading Level

Although at this point most kids are reading chapter books that are no longer labeled with a reading level, I wanted to give you some tools in case you feel the need to further assess what your child is reading.

• 4th Grade Book List  – 3.3-5.5 Book Level, O-T Guided Reading, 600-850 Lexile
• 5th Grade Reading List –  5.0-7.4 Book Level, S-W Guided Reading, 800-1000 Lexile
• 6th Grade 6.7-8.6 Book Level, V-Y Guided Reading, 950-1050 Lexile
• 7th &8th Grade 8.0-9.0 Book Level, X-Z Guided Reading, 1035-1100 Lexile

Find out any Books Reading Level

You can find out any books reading level (Lexile, library Book Level, and Scholastic Guided Reading) by checking AR Book Finder.

Free Printable Reading Logs

• Monthly Reading Log – this free printable has ‘traditional’ monthly themes
• Bookshelf Free Printable Reading Logs – super cute and fun for kids of all ages!
• Pencil Free Printable Reading Logs -print reading worksheet and color a pencil for each book you read
• Frozen Free Printable Reading Logs – kids will have fun tracking their reading and the books they’ve read with this motivating free printable for kids of all ages
• Princess Free Printable Reading Logs – students will have fun tracking their reading with these free printable reading logs
• Super Hero Free Printable Reading Logs – using a favorite theme of kids will encourage kids to read
• Cars Free Printable Book Logs – children will have fun tracking the books they’ve read with these clever free reading log
• Summer Free Printable Reading Logs – students will be motivated to read this summer with these ideas
• Reading Comprehension Bookmarks – this is a great tool for making sure kids are understanding what they are reading
• Reading Levels by Grade – how to pick the right books for every reading level and tons of printable book lists too

Book Report Idea

Looking for other ways to help kids work on reading comprehension and summarizing a book they read? Try these free resources:

• Handy Reading Comprehension Bookmarks (any book: fiction or non fiction)
• Book Report Template
• Book Report for Kids
• Pizza Book Report Idea
• Sandwich Book Report Idea
• 26 more clever Book Report Ideas
• Library Scavenger Hunt – help kids learn to navigate a library, the Dewey decimal system, book genres, and so much more with this pack of free printable scavenger hunts for kids!
• Bookshelf Reading Log – to help encourage kids to read!

Plus, here are some great ideas for Creating a Reading Nook where kids will want to curl up and read a book!

You may also like

May 2, 2018

December 8, 2020

August 5, 2021

November 2, 2015

March 10, 2020

August 30, 2021

August 29, 2020

September 25, 2015

About the author

Beth Gorden

Beth Gorden is the creative multi-tasking creator of 123 Homeschool 4 Me. As a busy homeschooling mother of six, she strives to create hands-on learning activities and worksheets that kids will love to make learning FUN! She has created over 1 million pages of printables to help teach kids ABCs, science, English grammar, history, math, and so much more! Beth is also the creator of 2 additional sites with even more educational activities and FREE printables - www.kindergartenworksheetsandgames.com and www.preschoolplayandlearn.com

L1, L2 and L3 cache. Definition - Iron on DTF

24568 views

The original is here.

Any computer processor, cheap laptop or million dollar server has a cache everywhere. And it has several levels.

Must be an important component, otherwise why is it there? What does the cache do, and why does it need several levels? What does 12-position associativity even mean?

What is a cache?

In a nutshell: This is a small but very fast memory that sits next to the logical blocks of the processor.

But of course we want to know a lot more about the cache...

Imagine an imaginary magical storage system: it's unrealistically fast, it can handle an infinite number of concurrent operations, and it always keeps data safe. If at least something remotely similar to this existed, then the design of processors would be much simpler.

The processor would only need logic modules for addition, multiplication, etc., and a system to handle the data transfer. This is due to the fact that our theoretical data storage system can send and receive all the necessary numbers instantly; none of the logical blocks will be waiting for data transfer.

But as we all know, there is no magic storage technology. Instead, we have hard drives (HDD) or solid state drives (SSD) and even the best of them are not capable of handling all the data transfers required by a conventional processor.

Great data storage elephant.

The reason modern processors are so fast is that they only need one clock cycle to add two 64-bit integer values ​​together. For a chip with a frequency of 4 GHz, this process will take only 00000000025 seconds, or a quarter of a nanosecond.

Meanwhile, hard drives take thousands of nanoseconds to find the data, not to mention that it still needs to be transferred. And solid-state drives - tens or hundreds of nanoseconds.

Disks of this kind cannot be built into the processor, this is understandable. Otherwise, they would be physically separated. This, in turn, would only increase the time for data transfer.

The second great data storage elephant, unfortunately.

Therefore, we need another storage system that sits between the processor and the main storage. It needs to be faster than a disk, as well as be able to process a lot of data at the same time, and be much closer to the processor.

Well, we already have such a system - random access memory (RAM). And this is its main task.

Virtually all "RAM" consists of dynamic random access memory (DRAM). It is much faster than any other disk.

Although DRAM is very fast, the amount of memory leaves much to be desired.

Micron's largest DDR4 memory chips capable of storing 32 Gb or 4 GB of data. At the same time, the most capacious hard drives have a capacity of 4000 times more.

Thus, although we have increased the data transfer rate, we need to understand what is required for the processor in the first place, because the memory is very limited. These solutions are handled by hardware and software.

At least DRAM can be produced in a chip package (embedded DRAM). But the processors are quite small, so there is no way to insert a lot of memory.

10 MB RAM. To the left of the Xbox 360 GPU.

The vast majority of DRAM is located right next to the processor, which in turn is connected to the mat. board. The closest component to the processor, and yet not fast enough.

DRAM still takes about 100 nanoseconds to find data, but it is capable of transmitting it at billions of bits per second. It seems that we need another link between the processor and DRAM.

SRAM (Static Random Access Memory) enters the scene. Where DRAM uses microscopic capacitors to store data as an electrical charge, SRAM uses transistors. And they can run almost as fast as logic modules in a processor (about 10 times faster than DRAM).

SRAM has a flaw, and again it's about size.

Transistor memory takes up much more space than DRAM. 4GB DDR4 is equivalent to only 100MB SRAM. But, since the design of the CPU is similar to SRAM, it can be built into the processor itself, located as close as possible to the logical devices.

Each time you increase the speed, the storage capacity decreases. We could keep adding more sections, each one faster but smaller.

So we've come to a more technical definition of what a cache is: These are a few blocks of SRAM that are located inside the processor. They are used to keep the logical blocks busy by sending and storing data at ultra-fast speeds. Satisfied? Well, good. From now on, things get a lot more complicated!

Cache: multilevel parking

As we said, the cache is necessary because the processor does not have a magic storage system that can satisfy the data needs of the logic modules. Modern CPUs and GPUs contain a number of SRAM blocks that are organized into a hierarchy, a sequence of caches that are ordered as follows:

In the image above, the processor is represented by a black dotted box. The ALU (Arithmetic Logic Unit) is on the left. This structure powers the processor and handles the math. Technically, it's not a cache. The closest memory level to the ALU are the registers (they are grouped into a register file).

Each contains a single number, such as a 64-bit integer. Its value can be a piece of data about something, a specific instruction code, or a memory address of some other data.

The register file in the desktop processor is very small - for example, in the Intel Core i9-9900K there are two "banks" in each core. One for integers, total 180 64-bit registers. Another register file for vectors (small arrays of numbers), 168 256-bit entries. Thus, the total register file for each core is a little less than 7 KB. By comparison, the Nvidia GeForce RTX 2080 Ti streaming multiprocessor (GPU core equivalent) register file size is 256 KB.

Registers are SRAM, like cache, but they are as fast as the ALU they serve, moving data in one clock cycle. But they are not designed to store very large amounts of data (only one part), so there are always several large blocks of memory nearby: this is the 1st level cache.

Intel Skylake processor. An enlarged image of one of the nuclei.

The above image is an enlarged view of one of the Intel Skylake processor cores.

ALU and registry files are visible on the left. They are highlighted in green. At the top of the photo, in the middle, L1 cache is marked in white. It doesn't have much information, only 32 kB, but like registers, it's very close to logical blocks and runs at the same speed as them.

Another white rectangle indicates the second level 1 instruction cache, also 32 kB. As the name suggests, it stores various instructions that will be divided into smaller, so-called micro operations (usually labeled as µops). All of them will be transferred to the ALU. They also have a cache, L0, since it is smaller (only 1500 operations) and closer than the L1 cache.

You might be wondering why these SRAM blocks are so small? Why aren't they measured in megabytes? In sum, the data and instruction caches take up almost as much space on the chip as the main logic blocks. Therefore, increasing their volume would increase the overall size of the matrix.

But the main reason why they contain several KB is that the time required to find and retrieve data increases as the amount of memory increases. The L1 cache needs to be really fast, and so a trade-off between size and speed needs to be made. At best, it takes about 5 cycles (longer for floating point values) to get the data out of this cache ready for use.

L2 cache in Skylake.

If this were the only cache in the processor, its performance would suddenly come to a standstill. So they have another level of memory built into the core: the L2 cache. This is a shared block of memory that stores instructions and data.

It is always slightly larger than level 1: AMD Zen 2 processors, for example, contain up to 512 kB, so the lower level caches are in good condition. However, the additional size incurs a delay in retrieving and transferring data from this cache. It takes about twice as long as in L1.

Remembering the Intel Pentium, then the L2 cache was a separate chip that was located on a small plug-in board (for example, RAM DIMM), or was built into the motherboard. In the end, L2 did get into the processor case. Integration into the processor matrix, based on Pentium III and AMD K6-III chips.

Further development entailed another layer to support other lower levels, and this happened due to the growth of multi-core processors.

Intel Kaby Lake processor.

In this image of Intel Kaby Lake, 4 cores are shown in the middle left (the integrated GPU occupies almost half of the die, on the right). Each core has its own set of level 1 and 2 caches (highlighted in white and yellow, respectively), but they also have a third set of SRAM blocks.

The L3 cache, although it surrounds one core, is completely separate from the others. Each of them can get free access to the contents of someone else's cache of the 3rd level. It is much larger (from 2 to 32 MB), but also much slower, averaging 30 cycles, especially if the kernel needs to use data that is in a cache block that is some distance away.

Below we see one of the AMD Zen 2 cores: 32 KB L1 cache (white), 512 KB L2 cache (yellow) and a huge 4 MB L3 cache block (red).

AMD Zen 2. One of the cores.

Stop. How can 32 kB physically take up more space than 512 kB? If L1 contains so little data, why is it so much larger than L2 or L3 cache?

More than just a number

The cache improves computer performance by speeding up the transfer of data to LUNs and by storing a copy of frequently used instructions and data nearby. The information stored in the cache is divided into two parts: the data itself and the place where it was originally located in system memory / storage - this address is called the cache tag.

When the processor performs an operation to read or write data from or to memory, it starts by checking the tags in the level 1 cache. If the desired tag is present, then access to this data can be obtained almost immediately. Mismatches occur when the required tag is not at the lowest cache level.

Thus, a new tag is created in the L1 cache, and the rest of the processor takes over the search for data for this tag, through other cache levels (up to the main drive, if necessary). But in order to make room in the L1 cache for this new tag, something else must be loaded into L2.

This results in almost constant data shuffling, all achieved in just a few clock cycles. The only way to achieve this is to have a complex structure around SRAM to manage the data. To put it another way: if the processor core consisted of only one ALU, then the L1 cache would be much simpler, but since there are dozens of them (many of which will pass through two threads with instructions), the cache requires many connections to continue working.

To check the cache in your own processor, you can use free programs such as CPU-Z. But what does all this information mean? An important element is the associative set of labels - it's all about the rules applied when copying data blocks from system memory to the cache.

The above information is from Intel Core i7-9700K. Its level 1 caches are broken into 64 small blocks called sets, and each of these is further broken down into cache lines (64 bytes in size). An associative set means that a block of data from system memory is mapped to the cache line in one specific set, and not anywhere else.

"x8" tells us that one block can be associated with 8 cache lines in the set. The higher the level of associativity (i.e., the more "ways"), the more likely it is to get a cache hit while the processor is looking for data, and also reduces the number of errors caused by cache misses. The disadvantages include: overall complexity, increased power consumption, and reduced performance as more cache lines must be processed to obtain a data block.

Cache L1+L2 inclusive. L3 cache memory of the victim. Write-back policy, even ECC (error-correcting memory).

Victim cache or Victim buffer (literally Victim cache) is a small specialized cache that stores those cache lines that were recently ousted from the main microprocessor cache when they were replaced.

Another aspect of cache complexity is how data is stored at different levels. The rules are set in a so-called inclusion policy. For example, Intel Core processors have a fully inclusive L1+L3 cache. This means that the same data on the first level can also be on the third. This may seem like a waste of valuable cache memory, but there is a major benefit: if the processor misses a tag lookup at a lower level, it doesn't have to look it up at a higher level.

On the same processors, the L2 cache is not inclusive: any data stored there is not copied to any other level. This saves space, but results in the processor's memory system having to look for the missing tag in L3 (which is always much larger). The victim cache is similar, but it is used to store information that comes from a lower level - for example, AMD Zen 2 processors use the L3 victim cache, which simply stores data from L2.

There are other caching policies, such as when data is written to the cache and main system memory. This is called a write policy, and most modern processors use a write-back cache: when data is written to cache memory, there is a delay before system memory is updated with a copy of that cache. For the most part, this pause lasts as long as the data remains in the cache - only after loading does the RAM receive information.

Nvidia GA100 GPU equipped with L1 cache (20MB) and L2 cache (40MB).

For processor designers, choosing the size, type, and policy of caching is a balancing act between advanced chip capabilities and overall increased complexity and required die space. If it were possible to create a 20MB, 1000-way fully associative L1 cache, and not have the chip become the size of Manhattan (and consume the same amount of power), then everyone would have computers with these processors!

The lowest level of caching in modern processors hasn't changed much in the last decade. However, the L3 cache continues to grow in size. Ten years ago, if you were lucky enough to own a $999 Intel i7-980X, you could get 12MB of L3 cache. For half that amount today, you get 64 MB.

Cache, in a nutshell: an absolutely necessary and amazing technology. We haven't looked at other types of caches in the CPU and GPU (such as the TLB or texture cache), but since they all follow a simple structure and level pattern, you won't find it hard to figure them out.

Did you have a computer with a separate L2 cache on the motherboard? What about those Pentium II and Celeron processors (specifically the 300a) that came as daughterboards? Can you remember your first shared L3 processor? Tell us about it in the comments.

NAND vs DRAM | Network Solutions/LAN Magazine

Prices for DRAM and NAND memory continue to rise as demand for these products outstrips production volumes. What attracts customers and how does one type of memory differ from another?

Enterprise-class SSDs typically use NAND flash technology, although sometimes even data storage uses DRAM memory modules, and some companies try to combine both technologies in their system architectures.

NAND flash uses a NOT AND gate and, like many other types of memory, stores data in an array of cells, where each cell contains one or more bits of data. Dynamic Random Access Memory (DRAM), a type of volatile semiconductor random access memory (RAM), is the most widely used RAM in modern computers.

Micron Technology expects the memory market to grow 2.5 times faster than the rest of the semiconductor industry over the next three to five years. But if we analyze the history of growth in memory chips sales (see Figure 1), we can see that each peak was followed by a sharp decline, although the depth of the decline was reduced with each new cycle, as the market consolidated and demand for memory diversified from PCs to smartphones. With further diversification, this market will become less volatile.

The key characteristics of DRAM SSD and NAND SSD are performance, durability and of course cost. But the main difference lies elsewhere.

ENERGY DEPENDENCE: PROBLEM AND SOLUTIONS

One of the main advantages of NAND SSD is non-volatility, that is, data is retained in memory even when the power is turned off. DRAM does not have this property, but this disadvantage can be compensated by the presence of an external UPS or a built-in battery, which is equipped with some systems and even DRAM cards.

There is also NVRAM memory, where NV stands for non-volatile. A non-volatile module with "dual" onboard NVDIMM memory combines flash memory and DRAM. In the event of a power failure, the capacitor allows data to be copied from the DRAM to the module's flash memory, and when normal operation is restored, the data is copied back to the DRAM.

For example, Micron's NVDIMM-N modules (see Figure 2) have an FPGA processor on the rail that copies data to SLC NAND in the event of a power failure, which is then provided by a supercapacitor.

Fig. 2. In 2017, Micron introduced 32GB NVDIMM-N modules. They run at DDR4-2933 and are a combination of ECC DRAM and NAND. The latter serves only for data backup

Combining DRAM with a capacitor and flash memory can result in an efficient write cache or highly reliable server memory that can withstand power failures. Conceptually and architecturally, these storages are well combined with other non-volatile drives - HDD hard drives (see Figure 3).

Such memory modules, called NVDIMM-N, can be used in database servers and file storage. NVDIMM-F modules use only NAND memory, and although they have lower performance, they are non-volatile "by default" and retain data in the event of a power failure without any additional technical solutions.

PERFORMANCE

DRAM, as the mainstream RAM technology, has balanced read/write performance and is noticeably superior to NAND flash, especially in write operations. However, the cost of DRAM is much higher.

NAND-based SD is great for read-centric applications, delivering high I/O IOPS but slower write performance. This is due to the fact that in order to write a new block of data, it is necessary to completely delete the previous block.

Nevertheless, the write performance of NAND drives is still significantly higher than that of mechanical disks, and NAND device developers have spent a lot of effort and money on improving write optimization algorithms. In addition, it makes sense to compare technologies when applied to specific applications.

DURABILITY

The lifetime of NAND flash should not be judged by time of use, but by the number of operations performed. As a result of erasing and writing data, its gradual degradation occurs at the level of individual cells, which affects the overall performance and available capacity of the device. While consumer NAND drives are rated for 3,000-10,000 writes, enterprise-class flash drives can withstand up to 100,000 cycles. DRAM is 100 times faster than NAND and lasts 100 times longer.

So, unlike DRAM, flash memory wears out quite quickly with heavy use. Sometimes drives will initially have more capacity than vendors claim to help offset the performance and capacity drops. And to reduce the rate of degradation, more and more complex recording algorithms are used.

DRAM is also prone to hardware failures, and time-tested methodologies are used to compensate or correct them. DRAM does not have a write resource, but over time it degrades. Errors can be caused by a large number of factors, including overheating, prolonged use, defects, etc.?

As one field study of DRAM memory errors showed, nearly a third of all machines and more than 8% of DIMMs had at least one correctable error per year ("DRAM errors in the wild: a large-scale field study" ). On some platforms, almost half of the systems experienced correctable errors, although on average only about 1. 3% of systems were affected by uncorrectable errors (for some, this figure was 2-4%).

Error correction and detection technology comes to the rescue. The most common option is error-correcting code (ECC) memory. Another option - Dell Reliable Memory Technology PRO (RMT PRO) - is similar in concept to hard drive error correction technology. It allows you to identify fatal errors and multi-bit correctable errors in the DIMM and correct the problem. When rebooting, RMT PRO marks the defective portion of an individual DIMM, reports the defect and the location of the bad DIMM portion to the BIOS, and removes these bad cells and a small number of adjacent cells from the system's used memory pool.

What is more durable - DRAM or NAND? Both products are guaranteed to work for many years. Many NAND manufacturers provide five-year warranties, some up to 10 years. Individual DRAM-based drives have similar characteristics. It is difficult to single out any significant difference here.

USAGE SCENARIOS

Vendors typically specialize in either DRAM or NAND devices, but some vendors are starting to offer both. DRAM is most often positioned as a high-performance cache memory or as the first (fastest) level in tiered data storage (tearing) systems.

In hybrid storage pools, NAND complements DRAM. Auto-tiring software can dynamically move hot data to fast (and more expensive) SSDs from slower (but larger and relatively cheap) hard drives (see Figure 4).

Analysts believe that this solid-state memory is likely to be in demand in data centers. Growth in transaction volumes, cloud computing, big data analytics, and next-generation workloads will require increased performance. Therefore, this technology will be especially useful for data centers and, to a lesser extent, for PCs.

NAND flash memory will be used for streaming data storage, batch processing, analytics tasks with database management systems. This will require the queue to grow to about 32 or more pending read/write operations.

The demand for DRAM and NAND memory is spurred on by the release of new smartphone models, the rapidly gaining popularity of cryptocurrency mining, the announcement of new processors from AMD and Intel, as well as new PCs based on them, which leads to higher prices. However, they may stabilize thanks to additional chip production launched by Samsung and SK Hynix this year.

Most IT organizations can benefit from a combination of DRAM and NAND based on architectural feasibility and cost of the solution (see Figure 5). However, in order to optimize DRAM and NAND deployments, it is useful to understand how these products differ and evaluate their prospects.

Fig. 5. Back in 2004, the cost of NAND caught up with the cost of DRAM and continued to decline until recently

OUTLOOK 3D NAND

Both types of memory continue to evolve, with DRAM developers increasing the capacity and clock speed of memory modules, and NAND manufacturers moving towards bulk packaging (3D NAND).

For example, Intel and Micron are already setting up production of 64-layer 3D NAND memory, as well as continuing to jointly develop and manufacture 3D XPoint non-volatile memory, which can increase its competitiveness. The NAND 3D XPoint memory announced by Intel and Micron in 2015 is produced by their joint venture IM Flash Technologies (see table).

3D XPoint offers better performance and durability than NAND, and sits somewhere between DRAM and NAND (see table). The advent of 3D XPoint will not lead to widespread replacement of DRAM in servers, but will reduce costs by replacing part of the RAM, as well as increase the performance of NAND solid state drives.

While DRAM currently costs about $5 per gigabyte, NAND costs about 25 cents. According to Gartner, 3D XPoint will cost about $2.40 per gigabyte for large batches, which is much more expensive than NAND, and this state of affairs will continue until at least 2021.

Intel and Micron do not provide details on the technology involved. It is assumed that 3D XPoint is a type of phase change memory (PCM), since Micron has already developed such a technology (with similar properties).

3D XPoint technology delivers up to 10 times the performance of "regular" NAND (when using the PCIe/NVMe interface), while being up to 1,000 times more durable with over a million write cycles, essentially a lifetime warranty.

For comparison, today's NAND memory is designed for 3-10 thousand erase-write cycles. With the help of software for wear assessment and error correction, the number of cycles can be increased, but a million write cycles is still not achievable.

The low latency of 3D XPoint (a thousand times less than that of NAND drives) allows products based on this technology to be used for tasks characterized by high I/O load, such as transaction processing systems (see Figure 6).

3D XPoint aims to fill a gap in the data center's memory and storage hierarchy, which includes SRAM (processor-based cache), DRAM (random access memory), NAND (SSD), hard drives, tape, and optical disks. It occupies an intermediate position between DRAM and non-volatile NAND flash memory.

Intel calls its version of 3D XPoint technology Optane memory (see Figure 7). Optane is designed to serve the hottest data in the storage hierarchy, or even increase the capacity of RAM. For example, it can be used to analyze current datasets in real time, or to store and update records.

In 2017, Intel began shipping products based on new technology: the 16GB/32GB Intel Optane Module for PCs and the 375GB Intel Optane SSD DC P4800X Module. This first 3D XPoint SSD can perform up to 550K read IOPS and 500K write IOPS with a queue depth of 16 or less. Like DRAM, 3D XPoint supports byte addressing, while NAND addressing occurs at the block level (see Figure 8).

According to IDC analysts, the introduction of 3D XPoint as the new storage layer is a major technological breakthrough, one of the most important since the advent of large-scale cloud data centers. Meanwhile, according to Intel, Optane-based products can be successfully used not only in data centers, but also in desktop computers to speed up data access.

The Intel Optane Module for PC functions as a cache memory to help speed up any SATA storage device on the 7th Gen Intel Core i platform. Intel claims it cuts PC boot time in half and improves overall system performance by 28%.

The DC P4800 is most effective in applications with random read/write operations and in this case acts as an extension to server DRAM. Optane performs well for random reads and writes.

DC P4800 SSD 375 GB per GB is about $4.05. The read speed of this device is 550 thousand IOPS using 4K blocks with a queue depth of 16. The sequential read-write speed is up to 2.4 and 2 GB / s, respectively.

In comparison, a NAND-based SSD, such as the 400GB Intel DC P3700, sells for $645, or $1.61 per GB. The P3700 delivers up to 450k IOPS 4K block reads at up to 128 sequential read/write queue depths (up to 2. 8 and 1.9GB/s respectively).

The Intel 3D XPoint Optane SSD has a read/write latency of less than 10µs, which is much lower than many NAND-based SSDs that range between 30µs and 100µs. Intel is considering two main use cases for the Optane DC P4800X (see Figure 9).

Intel plans to release Optane SSDs in 750GB and 1.5TB capacities with PCIe/NVMe and U.2 interfaces, and in addition, the company plans to ship Optane in the form of DRAM-style DIMMs.

Previously, the memory hierarchy was the following sequence: cache, main RAM, and disk. Hard drives have always been the biggest problem with this approach: access latencies are measured in milliseconds, orders of magnitude higher than DRAM. NAND flash has significantly lower latency than hard drives, but there is still a significant gap between NAND and DRAM. Intel Optane memory can fill the gap between DRAM and NAND, similar to how NAND sits in between DRAM and a conventional hard drive in a modern system.

Another advantage of Optane is that it provides similar performance at different queue depths. SSDs tend to work faster the greater the queue depth.

Micron also intends to gradually increase sales of its QuantX product and move to mass production in 2019. It positions QuantX SSDs as data center products, but also develops consumer-grade 3D NAND. For the end user, this means being able to analyze more data and do it in real time.

As 3D XPoint sales grow and production scales up, these drives may partially replace DRAM modules. They can be used for write caching or as a replacement / extension of RAM. In addition, for some workloads, access speed is less important than being able to store huge amounts of data in memory.

Micron announced that XPoint memory density is ten times higher than commercial DRAM products. This is true when compared to 30 nm class DRAM products, since most of these products from major DRAM manufacturers have a memory density of 0.06 GB/mm2. XPoint's first commercial product has three times the memory density of Samsung 1x DRAM, or six times that of Micron 20nm DRAM.

Gartner predicts that 3D XPoint technology will be widely used in data centers as early as the end of 2018. The data center ecosystem will have to adapt to new memory, including new chipsets and applications.

NEWS AND PLANS

The latest versions of 3D NAND contain up to 72 layers of flash memory, and manufacturers are already designing products with 96 layers (which may appear this year), and later with 128 layers. In addition, 3-bit cells (TLC) NAND are expected to be replaced by 4-bit cells (QLC). This will increase memory density and reduce manufacturing costs.

A year ago, the Chinese company Yangtze Memory Technologies announced plans to launch the production of DRAM chips with the 18-20 nm process technology and 32- and then 64-layer 3D NAND memory modules from 2018. This will allow it to compete with Micron, Samsung and SK Hynix. By 2025, China plans to expand production capacity for the manufacture of memory modules. Toshiba also intends to increase the output of 64-layer NAND memory. SK Hynix is ​​moving from 48-layer NAND to 72-layer NAND.

K Hynix announced the completion of the development of SATA SSDs up to 4TB, which uses 3D NAND memory chips with a capacity of 512GB, consisting of 72 layers. The sequential read speed in the new SSDs reaches 560 MB / s, and writes - 515 MB / s. With random access, the read speed can be 98K, and writes - 32K IOPS. In addition, the company is developing a PCIe SSD based on 72-layer memory with a capacity of more than 1TB. Their characteristics are 2700/1100 MB / s for sequential operations and 230/350 thousand IOPS for random read / write access, respectively.

In February, the Russian GS Group announced the start of mass production of SSDs in the Kaliningrad region. As stated, these 2.5" SATA drives are based on 3D NAND flash memory from leading manufacturers. Until the end of the year, it is planned to expand the line of SSDs with models up to 1 TB. The first - with a capacity of 256 GB - has a sequential read and write speed of 550 and 450 MB / s, respectively. And these are just some of the latest innovations (see Figure 10). Their appearance is facilitated by high demand from manufacturers of smartphones and servers for data centers.

Samsung's DRAM modules are manufactured using an 18nm process. Micron and SK Hynix are planning to implement 10nm technology standards, but there are many hurdles to overcome along the way. Meanwhile, Samsung is already mastering the 7nm process technology.

amsung electronics remains the market leader in flash memory. This year, it aims to accelerate the launch of high-density NAND products, expand the supply of high-capacity drives in the entry and mid-range segment, as well as enterprise-class drives with PCIe and NVMe interfaces.

The second place is occupied by Toshiba, which has focused on the supply of solid-state drives with a PCIe interface. The company intends to increase the production of NAND flash memory and increase the capacity for the production of 64-layer 3D NAND chips.

The leaders are followed by Western Digital, Micron, SK Hynix and Intel. All of them are successfully increasing sales and developing production for the production of 3D NAND memory chips.

At the same time, the development of conventional NAND flash memory will continue until at least 2025. Flash memory technologies are evolving at such a rapid pace that the whole concept of storage is changing dramatically (see Dmitry Ganzhi's article "Flash Time, or Towards Universal Memory" in the March 2017 issue of the Journal of Network Solutions / LAN).

Learn more

• 
  Dramatic story ideas
• 
  Leveled reading passage
• 
  What did little jack horner eat
• 
  Creative ways of teaching vocabulary
• 
  Good adjectives for students
• 
  What does cooperative play mean
• 
  Skills for kids
• 
  Fun kid girl games
• 
  How to teach letters
• 
  Printable reading activities
• 
  Why do cows moo at night